The present invention relates to solid-state imaging apparatus, and more particularly relates to MOS solid-state imaging apparatus capable both of using a concurrent shutter operation mode and of suppressing a noise and a darkening.
In recent years, MOS (Metal Oxide Semiconductor) type image sensors are drawing attention. An occurrence of phenomenon concerning such MOS image sensors has become evident that, when a very large amount of light enters, such a portion (portion receiving large amount of light) is caused to look black as if there has been no incidence of light at all. This phenomenon is hereinafter referred to as “black sun phenomenon”. Methods have been proposed to suppress the black sun phenomenon.
FIG. 1 is a schematic circuit diagram showing an example of construction of prior-art MOS solid-state imaging apparatus as disclosed in Japanese Patent Application Laid-Open 2000-287131. The solid-state imaging apparatus according to this example has a pixel section where a plurality of unit pixels (pixel cells) are two-dimensionally arranged, each including: a photodiode PD1 for effecting photoelectric conversion; a memory FD for temporarily retaining photoelectric conversion signal electric charges that occur in a predetermined period at photodiode PD1; a transfer transistor M4 for transferring photoelectric conversion signal electric charges from photodiode PD1 to the memory FD; a reset transistor M2 connected at one end to a power supply VDD, for resetting memory FD and photodiode PD1; an amplification transistor M1 for amplifying and reading the voltage level of memory FD; and a row select transistor M3 for reading output of the amplification transistor M1 selectively out to vertical signal lines 3-1, 3-2. In the illustrated example, a portion consisting of 2×2 arrangement of 4 pixels P11 to P22 is shown as the pixel section.
The apparatus also includes: a vertical scanning section 2 from which reset control pulses φRST1, φRST2, transfer control pulses φTX1-1, φTX1-2, row select pulses φROW1, φROW2 are outputted to drive the unit pixels P11 to P22; biasing transistors M6 for flowing a constant current to the vertical signal lines 3-1, 3-2; and a bias current regulating voltage line VBIAS for determining the current value of the biasing transistors M6. It further includes a clipping circuit 10 consisting of: a clipping transistor M10 for clipping the vertical signal lines 3-1, 3-2 at a constant voltage; a clip voltage VREF; and a clipping circuit select transistor M11 for connecting the clipping transistor M10 to the vertical signal lines 3-1, 3-2 by means of a clip control pulse φCLIP. Also included is a noise suppressing section 11 consisting of: a clamp capacitor C1 connected to the vertical signal lines 3-1, 3-2; a hold capacitor C2 for retaining amount of change of voltage of the vertical signal lines 3-1, 3-2; a sample-and-hold transistor M15 for connecting between the clamp capacitor C1 and the hold capacitor C2 by means of a sample-and-hold pulse φSH; and a clamp transistor M14 for clamping the clamp capacitor C1 and hold capacitor C2 to a noise suppressing section reference voltage VB by means of clamp pulse φCL.
It furthermore includes: a column select transistor M13 for reading signal from the hold capacitor C2 of each column to a horizontal signal line 15; a horizontal scanning section 20 for outputting horizontal select pulses φH1, φH2 which are to drive the column select transistor M13; a horizontal signal line reset transistor M20 for resetting the horizontal signal line 15 to a horizontal signal line reset voltage VHR by means of a horizontal signal line reset pulse φHR; an output amplifier 16 for amplifying and reading potential of the horizontal signal line 15; and AD converter 30 provided within the same chip as or at the outside of the solid-state imaging apparatus, for converting analog signal from the output amplifier 16 into digital signal. It should be noted that the vertical scanning section 2 and horizontal scanning section 20 are controlled by control signal from a control section 70 and that various types of control pulses are sent out from the control section 70.
FIG. 2 is a timing chart for explaining operation of the prior-art solid-state imaging apparatus shown in FIG. 1. A description will be given below with noticing the signal read operation from pixel P11 located at the first column on the first row. The reset control pulse φRST1 of the first row is driven to H level to turn ON the reset transistor M2 of the first row so as to reset a detection signal of the memory FD. Also at the same time, the row select pulse φROW1 of the first row is driven to H level to turn ON the row select transistor M3 of the first row so as to cause a reset voltage Vrst of the unit pixel P11 to be outputted to the vertical signal line 3-1. Outputted onto the vertical signal line 3-1 then is voltage (Vrst−Vgs-M1), i.e. lowered from the reset voltage Vrst by a threshold voltage Vgs-M1 of the amplification transistor M1.
At this time, the clamp control pulse φCL and sample-and-hold pulses SH are driven to H level to turn ON the sample-and-hold transistor M15 and clamp transistor M14. The clamp capacitor C1 and the hold capacitor C2 are thereby fixed to the clamp reference voltage VB.
Next, after bringing the reset control pulse φRST1 to L level, the clamp control pulse φCL is brought to L level to turn OFF the clamp transistor M14. A voltage (Vrst−Vgs-M1−Vrn) containing reset noise Vrn (feed-through component and KTC noise of the reset transistor M2) of each pixel is thereby retained at the clamp capacitor C1, and the connecting line between the clamp capacitor C1 and the hold capacitor C2 is brought into floating state. Subsequently, the transfer control pulse φTX1-1 of the first row is driven to H level to turn ON the transfer transistor M4 of the first row. The photoelectric conversion signal electric charge accumulated at photodiode PD1 is thereby transferred to the memory FD, and the transfer control pulse φTX1-1 is brought to L level again. Since the potential of memory FD is changed by amount corresponding to the photoelectric conversion signal voltage Vsig, it attains (Vrst−Vrn−Vsig) so that an output voltage (Vrst−Vgs-M1−Vrn−Vsig) is outputted onto the vertical signal line 3-1.
At this time, since amount corresponding to change from the voltage retained at the clamp capacitor C1 is accumulated at the hold capacitor C2, voltage (VB−[C1/(C1+C2)]×Vsig) is accumulated at the hold capacitor C2.
A differential processing is thereby effected at the noise suppressing section 11 between the voltage after reset and the voltage after transfer of photoelectric conversion signal charge of the unit pixel P11. Extracted thereby is photoelectric conversion signal voltage Vsig where reset noise Vrn such as KTC noise and feed-through component due to the reset transistor M2 of each pixel, as well as threshold voltage Vgs-M1 of the amplification transistor M1 are removed.
Subsequently, the sample-and-hold control pulse φSH is to L level to turn OFF the sample-and-hold transistor M15. A photoelectric conversion signal component of photodiode PD1 with noise being removed is thereby retained at the hold capacitor C2. Finally, photoelectric conversion signal components retained at the hold capacitor C2 are sequentially read out onto the horizontal signal line 15 by means of horizontal select pulse φH1, φH2 outputted from the horizontal scanning section 20 and are extracted from the output amplifier 16. Further, a signal from the output amplifier 16 is converted into digital signal by the AD converter 30 which is located within the same chip or at the outside. Here the reading by the horizontal select pulse φH1, φH2 is to be effected after the reset processing of the horizontal signal line 15 by the horizontal signal line reset transistor M20.
When the reading of signals of the first row is complete, signals of the second row are similarly read out. If, however, an intense light such as reflection light of the sun enters the MOS image sensor as described above, the black sun phenomenon occurs so that such portion is caused to look black. Supposing for example that an intense light is incident on the pixel P21 at the first column on the second row, the output of the amplification transistor M1 after reset of memory FD normally becomes a constant voltage (Vrst−Vgs-M1−Vrn) in theory in the above described reset operation of the pixel P21. Due to the effect of electric charge leaking into memory FD as a result of the incidence of an intense light, however, a leaked-in component of electric charge Vleak occurs after bringing the reset control pulse φRST2 to L level. The voltage of the vertical signal line 3-1 is thereby attained as (Vrst−Vgs-M1−Vrn−Vleak). For this reason, the voltage clamped by the clamp capacitor C1 becomes lower than normal.
The voltage of memory FD, when lowered to a certain level, does not fall any further. For this reason, the voltage of the memory FD hardly changes when Vleak has become large, even when photoelectric conversion signal charge of PD1 of the pixel P21 is transferred to the memory FD by driving the transfer control pulse φTX1-2 of the second row to H level. There is thus hardly any change from the clamp voltage, and, as a result, the black sun phenomenon occurs when high-luminance light enters. To suppress such black sun phenomenon, a clipping circuit 10 is provided in the solid-state imaging apparatus shown in FIG. 1.
FIG. 3 is a timing chart for explaining operation when the clipping circuit 10 is activated to suppress the black sun phenomenon. It is supposed that an intense light has entered the pixel P21. At this time, when reset control pulse φRST2 is brought to L level, the electric charge leaked into memory FD is accumulated and at the same time drop in potential of memory FD by Vleak occurs so that potential of the vertical signal line 3-1 steadily falls. Here, when clip pulse φCLIP is maintained at H level, the clipping transistor M10 is turned ON if the potential of the vertical signal line 3-1 has fallen to a potential (VREF−Vgs-M10), i.e. threshold voltage Vgs-M10 of the clipping transistor M10 subtracted from the clip reference potential VREF. When the clipping transistor M10 is turned ON, an electric current is supplied from the clipping circuit 10 to the vertical signal line 3-1 so as to keep the potential of the vertical signal line 3-1. Accordingly, even when potential of the vertical signal line 3-1 has fallen, such potential is clipped to potential (VREF−Vgs-M10) by activating the clipping circuit 10. A sufficient difference voltage is then detected and the black sun phenomenon is suppressed by turning OFF the clamping transistor M14 so as to clamp the voltage (VREF−Vgs-M10) of the vertical signal line 3-1 at the clamp capacitor C1 and effecting differential processing with the voltage after transfer of photoelectric conversion signal.